dram refresh

基本解釋

The refresh cycles are usually performed by a peripheralcalled a DRAM controller.
刷新周期一般由一個(gè)叫DRAM控制器的外設(shè)完成。
It is mainly composed of DMA controller (82C37), interrupt controller (82C59), programmable interval timers(82C54), DRAM refresh control, wait state generator and system reset logic.
其內(nèi)部主要由DMA控制器（82C37）、中斷控制器（82C59）、可編程間隔計(jì)時(shí)器（82C54），DRAM刷新控制器，等待狀態(tài)產(chǎn)生器，系統(tǒng)重置電路組成。
Once data has been written in DRAM, charges stored in each capacitor must maintain more than the refresh time so that the information stored in each DRAM cell can be read out correctly.
數(shù)據(jù)一旦被寫(xiě)進(jìn)DRAM，每個(gè)小電容上電荷的存儲(chǔ)時(shí)間就必須大于DRAM的刷新脈沖時(shí)間，如果由于漏電流致使存儲(chǔ)的電荷丟失，就會(huì)導(dǎo)致數(shù)據(jù)讀取的誤操作。