dram refresh

基本解釋

The refresh cycles are usually performed by a peripheralcalled a DRAM controller.
刷新周期一般由一個叫DRAM控制器的外設(shè)完成。
It is mainly composed of DMA controller (82C37), interrupt controller (82C59), programmable interval timers(82C54), DRAM refresh control, wait state generator and system reset logic.
其內(nèi)部主要由DMA控制器（82C37）、中斷控制器（82C59）、可編程間隔計時器（82C54），DRAM刷新控制器，等待狀態(tài)産生器，系統(tǒng)重置電路組成。
Once data has been written in DRAM, charges stored in each capacitor must maintain more than the refresh time so that the information stored in each DRAM cell can be read out correctly.
數(shù)據(jù)一旦被寫進(jìn)DRAM，每個小電容上電荷的存儲時間就必須大於DRAM的刷新脈沖時間，如果由於漏電流致使存儲的電荷丟失，就會導(dǎo)致數(shù)據(jù)讀取的誤操作。